From 200d15479c0bc48471ee7b8e538ce33af990f82e Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Thu, 17 Jul 2014 22:09:10 +0300 Subject: add or1k (OpenRISC 1000) architecture port With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use. --- src/internal/or1k/syscall.s | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 src/internal/or1k/syscall.s (limited to 'src/internal') diff --git a/src/internal/or1k/syscall.s b/src/internal/or1k/syscall.s new file mode 100644 index 00000000..2ea0eb13 --- /dev/null +++ b/src/internal/or1k/syscall.s @@ -0,0 +1,13 @@ +.global __syscall +.type __syscall,@function +__syscall: + l.ori r11, r3, 0 + l.lwz r3, 0(r1) + l.lwz r4, 4(r1) + l.lwz r5, 8(r1) + l.lwz r6, 12(r1) + l.lwz r7, 16(r1) + l.lwz r8, 20(r1) + l.sys 1 + l.jr r9 + l.nop -- cgit v1.2.3-70-g09d2