Ensure TSan works on PowerPC and RISC-V.

Ported to GCC from compiler-rt.  Original patch at: https://github.com/chimera-linux/cports/blob/0f5c5be86e/main/llvm/patches/0008-compiler-rt-lsan-basic-musl-fixes-on-various-archs.patch

--- gcc-13.3.0/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp.old	2024-05-21 02:47:42.000000000 -0500
+++ gcc-13.3.0/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp	2024-08-05 07:52:22.981401062 -0500
@@ -29,6 +29,14 @@
 #include "sanitizer_procmaps.h"
 #include "sanitizer_solaris.h"
 
+#if defined(__powerpc__)
+#define DTP_OFFSET 0x8000
+#elif SANITIZER_RISCV64
+#define DTP_OFFSET 0x800
+#else
+#define DTP_OFFSET 0
+#endif
+
 #if SANITIZER_NETBSD
 #define _RTLD_SOURCE  // for __lwp_gettcb_fast() / __lwp_getprivate_fast()
 #endif
@@ -289,6 +297,7 @@
   return val;
 }
 
+#if SANITIZER_GLIBC
 uptr ThreadDescriptorSize() {
   uptr val = atomic_load_relaxed(&thread_descriptor_size);
   if (val)
@@ -303,6 +312,9 @@
   atomic_store_relaxed(&thread_descriptor_size, val);
   return val;
 }
+#else
+uptr ThreadDescriptorSize() { return 0; }
+#endif
 
 #if defined(__mips__) || defined(__powerpc64__) || SANITIZER_RISCV64
 // TlsPreTcbSize includes size of struct pthread_descr and size of tcb
@@ -392,6 +404,7 @@
     begin = (uptr)__tls_get_addr(mod_and_off);
 #endif
   }
+  begin -= DTP_OFFSET;
   for (unsigned i = 0; i != info->dlpi_phnum; ++i)
     if (info->dlpi_phdr[i].p_type == PT_TLS) {
       static_cast<InternalMmapVector<TlsBlock> *>(data)->push_back(
@@ -542,9 +555,11 @@
   else if (SANITIZER_FREEBSD)
     *size += 128;  // RTLD_STATIC_TLS_EXTRA
 #if defined(__mips__) || defined(__powerpc64__) || SANITIZER_RISCV64
+#  if SANITIZER_GLIBC
   const uptr pre_tcb_size = TlsPreTcbSize();
   *addr -= pre_tcb_size;
   *size += pre_tcb_size;
+#  endif
 #else
   // arm and aarch64 reserve two words at TP, so this underestimates the range.
   // However, this is sufficient for the purpose of finding the pointers to