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author | Szabolcs Nagy <nsz@port70.net> | 2016-01-24 20:51:34 +0000 |
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committer | Rich Felker <dalias@aerifal.cx> | 2016-01-24 19:07:35 -0500 |
commit | 2d14fa39b0e3c957ad4f7def033e40ea431ffcfb (patch) | |
tree | 6220e84a37ddd3efa60cd5a08c6d401073e6ed31 /arch/aarch64 | |
parent | b17fbd3520640745051d2fd9f1fd334ceb8b8783 (diff) | |
download | musl-2d14fa39b0e3c957ad4f7def033e40ea431ffcfb.tar.gz musl-2d14fa39b0e3c957ad4f7def033e40ea431ffcfb.tar.bz2 musl-2d14fa39b0e3c957ad4f7def033e40ea431ffcfb.tar.xz musl-2d14fa39b0e3c957ad4f7def033e40ea431ffcfb.zip |
fix aarch64 atomics to load/store 32bit only
a_ll/a_sc inline asm used 64bit register operands (%0) instead of 32bit
ones (%w0), this at least broke a_and_64 (which always cleared the top
32bit, leaking memory in malloc).
Diffstat (limited to 'arch/aarch64')
-rw-r--r-- | arch/aarch64/atomic_arch.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/aarch64/atomic_arch.h b/arch/aarch64/atomic_arch.h index 14fea03b..6b4f1a4d 100644 --- a/arch/aarch64/atomic_arch.h +++ b/arch/aarch64/atomic_arch.h @@ -2,7 +2,7 @@ static inline int a_ll(volatile int *p) { int v; - __asm__ __volatile__ ("ldaxr %0, %1" : "=r"(v) : "Q"(*p)); + __asm__ __volatile__ ("ldaxr %w0,%1" : "=r"(v) : "Q"(*p)); return v; } @@ -10,7 +10,7 @@ static inline int a_ll(volatile int *p) static inline int a_sc(volatile int *p, int v) { int r; - __asm__ __volatile__ ("stlxr %w0,%1,%2" : "=&r"(r) : "r"(v), "Q"(*p) : "memory"); + __asm__ __volatile__ ("stlxr %w0,%w1,%2" : "=&r"(r) : "r"(v), "Q"(*p) : "memory"); return !r; } |