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authorSzabolcs Nagy <nsz@port70.net>2016-10-09 20:42:02 +0200
committerRich Felker <dalias@aerifal.cx>2016-10-20 01:28:25 -0400
commitfe39aaae0eafdab3340ea9a4c4b275c3528b4d75 (patch)
tree2055dff0982e4ab83e1615c1c8cb50ca1e3e10f7 /arch/arm
parent5a05f67599ff06f9255aa4119cfecb85575d6e20 (diff)
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add bits/hwcap.h and include it in sys/auxv.h
aarch64, arm, mips, mips64, mipsn32, powerpc, powerpc64 and sh have cpu feature bits defined in linux for AT_HWCAP auxv entry, so expose those in sys/auxv.h it seems the mips hwcaps were never exposed to userspace neither by linux nor by glibc, but that's most likely an oversight.
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/bits/hwcap.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/bits/hwcap.h b/arch/arm/bits/hwcap.h
new file mode 100644
index 00000000..ac4edeac
--- /dev/null
+++ b/arch/arm/bits/hwcap.h
@@ -0,0 +1,29 @@
+#define HWCAP_SWP (1 << 0)
+#define HWCAP_HALF (1 << 1)
+#define HWCAP_THUMB (1 << 2)
+#define HWCAP_26BIT (1 << 3)
+#define HWCAP_FAST_MULT (1 << 4)
+#define HWCAP_FPA (1 << 5)
+#define HWCAP_VFP (1 << 6)
+#define HWCAP_EDSP (1 << 7)
+#define HWCAP_JAVA (1 << 8)
+#define HWCAP_IWMMXT (1 << 9)
+#define HWCAP_CRUNCH (1 << 10)
+#define HWCAP_THUMBEE (1 << 11)
+#define HWCAP_NEON (1 << 12)
+#define HWCAP_VFPv3 (1 << 13)
+#define HWCAP_VFPv3D16 (1 << 14)
+#define HWCAP_TLS (1 << 15)
+#define HWCAP_VFPv4 (1 << 16)
+#define HWCAP_IDIVA (1 << 17)
+#define HWCAP_IDIVT (1 << 18)
+#define HWCAP_VFPD32 (1 << 19)
+#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
+#define HWCAP_LPAE (1 << 20)
+#define HWCAP_EVTSTRM (1 << 21)
+
+#define HWCAP2_AES (1 << 0)
+#define HWCAP2_PMULL (1 << 1)
+#define HWCAP2_SHA1 (1 << 2)
+#define HWCAP2_SHA2 (1 << 3)
+#define HWCAP2_CRC32 (1 << 4)