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author | Rich Felker <dalias@aerifal.cx> | 2016-01-21 19:08:54 +0000 |
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committer | Rich Felker <dalias@aerifal.cx> | 2016-01-21 19:08:54 +0000 |
commit | 1315596b510189b5159e742110b504177bdd4932 (patch) | |
tree | 27159b7b95b944671454b11f36ee13308241f4b5 /arch/mips | |
parent | ce3e24eaae91e7a90f87eb7f1edea8df5942de11 (diff) | |
download | musl-1315596b510189b5159e742110b504177bdd4932.tar.gz musl-1315596b510189b5159e742110b504177bdd4932.tar.bz2 musl-1315596b510189b5159e742110b504177bdd4932.tar.xz musl-1315596b510189b5159e742110b504177bdd4932.zip |
refactor internal atomic.h
rather than having each arch provide its own atomic.h, there is a new
shared atomic.h in src/internal which pulls arch-specific definitions
from arc/$(ARCH)/atomic_arch.h. the latter can be extremely minimal,
defining only a_cas or new ll/sc type primitives which the shared
atomic.h will use to construct everything else.
this commit avoids making heavy changes to the individual archs'
atomic implementations. definitions which are identical or
near-identical to what the new shared atomic.h would produce have been
removed, but otherwise the changes made are just hooking up the
arch-specific files to the new infrastructure. major changes to take
advantage of the new system will come in subsequent commits.
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/atomic.h | 205 | ||||
-rw-r--r-- | arch/mips/atomic_arch.h | 61 |
2 files changed, 61 insertions, 205 deletions
diff --git a/arch/mips/atomic.h b/arch/mips/atomic.h deleted file mode 100644 index c82046a8..00000000 --- a/arch/mips/atomic.h +++ /dev/null @@ -1,205 +0,0 @@ -#ifndef _INTERNAL_ATOMIC_H -#define _INTERNAL_ATOMIC_H - -#include <stdint.h> - -static inline int a_ctz_l(unsigned long x) -{ - static const char debruijn32[32] = { - 0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13, - 31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14 - }; - return debruijn32[(x&-x)*0x076be629 >> 27]; -} - -static inline int a_ctz_64(uint64_t x) -{ - uint32_t y = x; - if (!y) { - y = x>>32; - return 32 + a_ctz_l(y); - } - return a_ctz_l(y); -} - -static inline int a_cas(volatile int *p, int t, int s) -{ - int dummy; - __asm__ __volatile__( - ".set push\n" - ".set mips2\n" - ".set noreorder\n" - " sync\n" - "1: ll %0, %2\n" - " bne %0, %3, 1f\n" - " addu %1, %4, $0\n" - " sc %1, %2\n" - " beq %1, $0, 1b\n" - " nop\n" - " sync\n" - "1: \n" - ".set pop\n" - : "=&r"(t), "=&r"(dummy), "+m"(*p) : "r"(t), "r"(s) : "memory" ); - return t; -} - -static inline void *a_cas_p(volatile void *p, void *t, void *s) -{ - return (void *)a_cas(p, (int)t, (int)s); -} - -static inline int a_swap(volatile int *x, int v) -{ - int old, dummy; - __asm__ __volatile__( - ".set push\n" - ".set mips2\n" - ".set noreorder\n" - " sync\n" - "1: ll %0, %2\n" - " addu %1, %3, $0\n" - " sc %1, %2\n" - " beq %1, $0, 1b\n" - " nop\n" - " sync\n" - ".set pop\n" - : "=&r"(old), "=&r"(dummy), "+m"(*x) : "r"(v) : "memory" ); - return old; -} - -static inline int a_fetch_add(volatile int *x, int v) -{ - int old, dummy; - __asm__ __volatile__( - ".set push\n" - ".set mips2\n" - ".set noreorder\n" - " sync\n" - "1: ll %0, %2\n" - " addu %1, %0, %3\n" - " sc %1, %2\n" - " beq %1, $0, 1b\n" - " nop\n" - " sync\n" - ".set pop\n" - : "=&r"(old), "=&r"(dummy), "+m"(*x) : "r"(v) : "memory" ); - return old; -} - -static inline void a_inc(volatile int *x) -{ - int dummy; - __asm__ __volatile__( - ".set push\n" - ".set mips2\n" - ".set noreorder\n" - " sync\n" - "1: ll %0, %1\n" - " addu %0, %0, 1\n" - " sc %0, %1\n" - " beq %0, $0, 1b\n" - " nop\n" - " sync\n" - ".set pop\n" - : "=&r"(dummy), "+m"(*x) : : "memory" ); -} - -static inline void a_dec(volatile int *x) -{ - int dummy; - __asm__ __volatile__( - ".set push\n" - ".set mips2\n" - ".set noreorder\n" - " sync\n" - "1: ll %0, %1\n" - " subu %0, %0, 1\n" - " sc %0, %1\n" - " beq %0, $0, 1b\n" - " nop\n" - " sync\n" - ".set pop\n" - : "=&r"(dummy), "+m"(*x) : : "memory" ); -} - -static inline void a_store(volatile int *p, int x) -{ - __asm__ __volatile__( - ".set push\n" - ".set mips2\n" - ".set noreorder\n" - " sync\n" - " sw %1, %0\n" - " sync\n" - ".set pop\n" - : "+m"(*p) : "r"(x) : "memory" ); -} - -#define a_spin a_barrier - -static inline void a_barrier() -{ - a_cas(&(int){0}, 0, 0); -} - -static inline void a_crash() -{ - *(volatile char *)0=0; -} - -static inline void a_and(volatile int *p, int v) -{ - int dummy; - __asm__ __volatile__( - ".set push\n" - ".set mips2\n" - ".set noreorder\n" - " sync\n" - "1: ll %0, %1\n" - " and %0, %0, %2\n" - " sc %0, %1\n" - " beq %0, $0, 1b\n" - " nop\n" - " sync\n" - ".set pop\n" - : "=&r"(dummy), "+m"(*p) : "r"(v) : "memory" ); -} - -static inline void a_or(volatile int *p, int v) -{ - int dummy; - __asm__ __volatile__( - ".set push\n" - ".set mips2\n" - ".set noreorder\n" - " sync\n" - "1: ll %0, %1\n" - " or %0, %0, %2\n" - " sc %0, %1\n" - " beq %0, $0, 1b\n" - " nop\n" - " sync\n" - ".set pop\n" - : "=&r"(dummy), "+m"(*p) : "r"(v) : "memory" ); -} - -static inline void a_or_l(volatile void *p, long v) -{ - a_or(p, v); -} - -static inline void a_and_64(volatile uint64_t *p, uint64_t v) -{ - union { uint64_t v; uint32_t r[2]; } u = { v }; - a_and((int *)p, u.r[0]); - a_and((int *)p+1, u.r[1]); -} - -static inline void a_or_64(volatile uint64_t *p, uint64_t v) -{ - union { uint64_t v; uint32_t r[2]; } u = { v }; - a_or((int *)p, u.r[0]); - a_or((int *)p+1, u.r[1]); -} - -#endif diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h new file mode 100644 index 00000000..b111c894 --- /dev/null +++ b/arch/mips/atomic_arch.h @@ -0,0 +1,61 @@ +#define a_cas a_cas +static inline int a_cas(volatile int *p, int t, int s) +{ + int dummy; + __asm__ __volatile__( + ".set push\n" + ".set mips2\n" + ".set noreorder\n" + " sync\n" + "1: ll %0, %2\n" + " bne %0, %3, 1f\n" + " addu %1, %4, $0\n" + " sc %1, %2\n" + " beq %1, $0, 1b\n" + " nop\n" + " sync\n" + "1: \n" + ".set pop\n" + : "=&r"(t), "=&r"(dummy), "+m"(*p) : "r"(t), "r"(s) : "memory" ); + return t; +} + +#define a_swap a_swap +static inline int a_swap(volatile int *x, int v) +{ + int old, dummy; + __asm__ __volatile__( + ".set push\n" + ".set mips2\n" + ".set noreorder\n" + " sync\n" + "1: ll %0, %2\n" + " addu %1, %3, $0\n" + " sc %1, %2\n" + " beq %1, $0, 1b\n" + " nop\n" + " sync\n" + ".set pop\n" + : "=&r"(old), "=&r"(dummy), "+m"(*x) : "r"(v) : "memory" ); + return old; +} + +#define a_fetch_add a_fetch_add +static inline int a_fetch_add(volatile int *x, int v) +{ + int old, dummy; + __asm__ __volatile__( + ".set push\n" + ".set mips2\n" + ".set noreorder\n" + " sync\n" + "1: ll %0, %2\n" + " addu %1, %0, %3\n" + " sc %1, %2\n" + " beq %1, $0, 1b\n" + " nop\n" + " sync\n" + ".set pop\n" + : "=&r"(old), "=&r"(dummy), "+m"(*x) : "r"(v) : "memory" ); + return old; +} |