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authorRich Felker <dalias@aerifal.cx>2016-04-03 10:42:37 +0000
committerRich Felker <dalias@aerifal.cx>2016-04-03 10:42:37 +0000
commit6d99ad91e869aab35a4d76d34c3c9eaf29482bad (patch)
treef8e7665f23b5067b5ca39d2e7a19f7132fc9e2e3 /arch/mips
parentc718f9fc1b4bd913eff10d0c12763f90b2bc487c (diff)
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add support for mips and mips64 r6 isa
mips32r6 and mips64r6 are actually new isas at both the asm source and opcode levels (pre-r6 code cannot run on r6) and thus need to be treated as a new subarch. the following changes are made, some of which yield code generation improvements for non-r6 targets too: - add subarch logic in configure script and reloc.h files for dynamic linker name. - suppress use of .set mips2 asm directives (used to allow mips2 atomic instructions on baseline mips1 builds; the kernel has to emulate them on mips1) except when actually needed. they cause wrong instruction encodings on r6, and pessimize inlining on at least some compilers. - only hard-code sync instruction encoding on mips1. - use "ZC" constraint instead of "m" constraint for llsc memory operands on r6, where the ll/sc instructions no longer accept full 16-bit offsets. - only hard-code rdhwr instruction encoding with .word on targets (pre-r2) where it may need trap-and-emulate by the kernel. otherwise, just use the instruction mnemonic, and allow an arbitrary destination register to be used.
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/atomic_arch.h27
-rw-r--r--arch/mips/pthread_arch.h9
-rw-r--r--arch/mips/reloc.h8
3 files changed, 34 insertions, 10 deletions
diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h
index ce2823b8..1248d177 100644
--- a/arch/mips/atomic_arch.h
+++ b/arch/mips/atomic_arch.h
@@ -1,12 +1,24 @@
+#if __mips_isa_rev < 6
+#define LLSC_M "m"
+#else
+#define LLSC_M "ZC"
+#endif
+
#define a_ll a_ll
static inline int a_ll(volatile int *p)
{
int v;
+#if __mips < 2
__asm__ __volatile__ (
".set push ; .set mips2\n\t"
"ll %0, %1"
"\n\t.set pop"
: "=r"(v) : "m"(*p));
+#else
+ __asm__ __volatile__ (
+ "ll %0, %1"
+ : "=r"(v) : LLSC_M(*p));
+#endif
return v;
}
@@ -14,26 +26,33 @@ static inline int a_ll(volatile int *p)
static inline int a_sc(volatile int *p, int v)
{
int r;
+#if __mips < 2
__asm__ __volatile__ (
".set push ; .set mips2\n\t"
"sc %0, %1"
"\n\t.set pop"
: "=r"(r), "=m"(*p) : "0"(v) : "memory");
+#else
+ __asm__ __volatile__ (
+ "sc %0, %1"
+ : "=r"(r), "="LLSC_M(*p) : "0"(v) : "memory");
+#endif
return r;
}
#define a_barrier a_barrier
static inline void a_barrier()
{
+#if __mips < 2
/* mips2 sync, but using too many directives causes
* gcc not to inline it, so encode with .long instead. */
__asm__ __volatile__ (".long 0xf" : : : "memory");
-#if 0
- __asm__ __volatile__ (
- ".set push ; .set mips2 ; sync ; .set pop"
- : : : "memory");
+#else
+ __asm__ __volatile__ ("sync" : : : "memory");
#endif
}
#define a_pre_llsc a_barrier
#define a_post_llsc a_barrier
+
+#undef LLSC_M
diff --git a/arch/mips/pthread_arch.h b/arch/mips/pthread_arch.h
index 8a499654..e5812655 100644
--- a/arch/mips/pthread_arch.h
+++ b/arch/mips/pthread_arch.h
@@ -1,12 +1,11 @@
static inline struct pthread *__pthread_self()
{
-#ifdef __clang__
- char *tp;
- __asm__ __volatile__ (".word 0x7c03e83b ; move %0, $3" : "=r" (tp) : : "$3" );
-#else
+#if __mips_isa_rev < 2
register char *tp __asm__("$3");
- /* rdhwr $3,$29 */
__asm__ __volatile__ (".word 0x7c03e83b" : "=r" (tp) );
+#else
+ char *tp;
+ __asm__ __volatile__ ("rdhwr %0, $29" : "=r" (tp) );
#endif
return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
}
diff --git a/arch/mips/reloc.h b/arch/mips/reloc.h
index 8c52df09..b3d59a45 100644
--- a/arch/mips/reloc.h
+++ b/arch/mips/reloc.h
@@ -1,5 +1,11 @@
#include <endian.h>
+#if __mips_isa_rev >= 6
+#define ISA_SUFFIX "r6"
+#else
+#define ISA_SUFFIX ""
+#endif
+
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define ENDIAN_SUFFIX "el"
#else
@@ -12,7 +18,7 @@
#define FP_SUFFIX ""
#endif
-#define LDSO_ARCH "mips" ENDIAN_SUFFIX FP_SUFFIX
+#define LDSO_ARCH "mips" ISA_SUFFIX ENDIAN_SUFFIX FP_SUFFIX
#define TPOFF_K (-0x7000)