add or1k (OpenRISC 1000) architecture port

With the exception of a fenv implementation, the port is fully featured.
The port has been tested in or1ksim, the golden reference functional
simulator for OpenRISC 1000.
It passes all libc-test tests (except the math tests that
requires a fenv implementation).

The port assumes an or1k implementation that has support for
atomic instructions (l.lwa/l.swa).

Although it passes all the libc-test tests, the port is still
in an experimental state, and has yet experienced very little
'real-world' use.

1 files changed, 154 insertions, 0 deletions

diff --git a/arch/or1k/syscall_arch.h b/arch/or1k/syscall_arch.h
new file mode 100644
index 00000000..aa1e623d
--- /dev/null
+++ b/arch/or1k/syscall_arch.h
@@ -0,0 +1,154 @@
+#define __SYSCALL_LL_E(x) \
+((union { long long ll; long l[2]; }){ .ll = x }).l[0], \
+((union { long long ll; long l[2]; }){ .ll = x }).l[1]
+#define __SYSCALL_LL_O(x) 0, __SYSCALL_LL_E((x))
+
+long (__syscall)(long, ...);
+
+#ifndef __clang__
+
+static __inline long __syscall0(long n)
+{
+	register unsigned long r11 __asm__("r11") = n;
+	__asm__ __volatile__ ("l.sys 1"
+			      : "=r"(r11)
+			      : "r"(r11)
+			      : "memory", "r3", "r4", "r5", "r6", "r7", "r8",
+				"r12", "r13", "r15", "r17", "r19", "r21",
+				"r23", "r25", "r27", "r29", "r31");
+	return r11;
+}
+
+static inline long __syscall1(long n, long a)
+{
+	register unsigned long r11 __asm__("r11") = n;
+	register unsigned long r3 __asm__("r3") = a;
+	__asm__ __volatile__ ("l.sys 1"
+			      : "=r"(r11)
+			      : "r"(r11), "r"(r3)
+			      : "memory", "r4", "r5", "r6", "r7", "r8",
+				"r12", "r13", "r15", "r17", "r19", "r21",
+				"r23", "r25", "r27", "r29", "r31");
+	return r11;
+}
+
+static inline long __syscall2(long n, long a, long b)
+{
+	register unsigned long r11 __asm__("r11") = n;
+	register unsigned long r3 __asm__("r3") = a;
+	register unsigned long r4 __asm__("r4") = b;
+	__asm__ __volatile__ ("l.sys 1"
+			      : "=r"(r11)
+			      : "r"(r11), "r"(r3), "r"(r4)
+			      : "memory", "r5", "r6", "r7", "r8",
+				"r12", "r13", "r15", "r17", "r19", "r21",
+				"r23", "r25", "r27", "r29", "r31");
+	return r11;
+}
+
+static inline long __syscall3(long n, long a, long b, long c)
+{
+	register unsigned long r11 __asm__("r11") = n;
+	register unsigned long r3 __asm__("r3") = a;
+	register unsigned long r4 __asm__("r4") = b;
+	register unsigned long r5 __asm__("r5") = c;
+	__asm__ __volatile__ ("l.sys 1"
+			      : "=r"(r11)
+			      : "r"(r11), "r"(r3), "r"(r4), "r"(r5)
+			      : "memory", "r6", "r7", "r8",
+				"r12", "r13", "r15", "r17", "r19", "r21",
+				"r23", "r25", "r27", "r29", "r31");
+	return r11;
+}
+
+static inline long __syscall4(long n, long a, long b, long c, long d)
+{
+	register unsigned long r11 __asm__("r11") = n;
+	register unsigned long r3 __asm__("r3") = a;
+	register unsigned long r4 __asm__("r4") = b;
+	register unsigned long r5 __asm__("r5") = c;
+	register unsigned long r6 __asm__("r6") = d;
+	__asm__ __volatile__ ("l.sys 1"
+			      : "=r"(r11)
+			      : "r"(r11), "r"(r3), "r"(r4), "r"(r5), "r"(r6)
+			      : "memory", "r7", "r8",
+				"r12", "r13", "r15", "r17", "r19", "r21",
+				"r23", "r25", "r27", "r29", "r31");
+	return r11;
+}
+
+static inline long __syscall5(long n, long a, long b, long c, long d, long e)
+{
+	register unsigned long r11 __asm__("r11") = n;
+	register unsigned long r3 __asm__("r3") = a;
+	register unsigned long r4 __asm__("r4") = b;
+	register unsigned long r5 __asm__("r5") = c;
+	register unsigned long r6 __asm__("r6") = d;
+	register unsigned long r7 __asm__("r7") = e;
+	__asm__ __volatile__ ("l.sys 1"
+			      : "=r"(r11)
+			      : "r"(r11), "r"(r3), "r"(r4), "r"(r5), "r"(r6),
+				"r"(r7)
+			      : "memory", "r8",
+				"r12", "r13", "r15", "r17", "r19", "r21",
+				"r23", "r25", "r27", "r29", "r31");
+	return r11;
+}
+
+static inline long __syscall6(long n, long a, long b, long c, long d, long e, long f)
+{
+	register unsigned long r11 __asm__("r11") = n;
+	register unsigned long r3 __asm__("r3") = a;
+	register unsigned long r4 __asm__("r4") = b;
+	register unsigned long r5 __asm__("r5") = c;
+	register unsigned long r6 __asm__("r6") = d;
+	register unsigned long r7 __asm__("r7") = e;
+	register unsigned long r8 __asm__("r8") = f;
+	__asm__ __volatile__ ("l.sys 1"
+			      : "=r"(r11)
+			      : "r"(r11), "r"(r3), "r"(r4), "r"(r5), "r"(r6),
+				"r"(r7), "r"(r8)
+			      : "memory",
+				"r12", "r13", "r15", "r17", "r19", "r21",
+				"r23", "r25", "r27", "r29", "r31");
+	return r11;
+}
+
+#else
+
+static inline long __syscall0(long n)
+{
+	return (__syscall)(n);
+}
+
+static inline long __syscall1(long n, long a)
+{
+	return (__syscall)(n, a);
+}
+
+static inline long __syscall2(long n, long a, long b)
+{
+	return (__syscall)(n, a, b);
+}
+
+static inline long __syscall3(long n, long a, long b, long c)
+{
+	return (__syscall)(n, a, b, c);
+}
+
+static inline long __syscall4(long n, long a, long b, long c, long d)
+{
+	return (__syscall)(n, a, b, c, d);
+}
+
+static inline long __syscall5(long n, long a, long b, long c, long d, long e)
+{
+	return (__syscall)(n, a, b, c, d, e);
+}
+
+static inline long __syscall6(long n, long a, long b, long c, long d, long e, long f)
+{
+	return (__syscall)(n, a, b, c, d, e, f);
+}
+
+#endif