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author | Rich Felker <dalias@aerifal.cx> | 2016-01-22 02:58:32 +0000 |
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committer | Rich Felker <dalias@aerifal.cx> | 2016-01-22 02:58:32 +0000 |
commit | 513c043694f500a01bd8d899ff73441aa7457a1f (patch) | |
tree | 50c4cc8fc40a4f847b94542559206bb2fb603529 /arch/powerpc | |
parent | 16b55298dc4b6a54d287d7494e04542667ef8861 (diff) | |
download | musl-513c043694f500a01bd8d899ff73441aa7457a1f.tar.gz musl-513c043694f500a01bd8d899ff73441aa7457a1f.tar.bz2 musl-513c043694f500a01bd8d899ff73441aa7457a1f.tar.xz musl-513c043694f500a01bd8d899ff73441aa7457a1f.zip |
overhaul powerpc atomics for new atomics framework
previously powerpc had a_cas defined in terms of its native ll/sc
style operations, but all other atomics were defined in terms of
a_cas. instead define a_ll and a_sc so the compiler can generate
optimized versions of all the atomic ops and perform better inlining
of a_cas.
extracting the result of the sc (stwcx.) instruction is rather awkward
because it's natively stored in a condition flag, which is not
representable in inline asm. but even with this limitation the new
code still seems significantly better.
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/atomic_arch.h | 52 |
1 files changed, 38 insertions, 14 deletions
diff --git a/arch/powerpc/atomic_arch.h b/arch/powerpc/atomic_arch.h index f014e3b8..f31566b2 100644 --- a/arch/powerpc/atomic_arch.h +++ b/arch/powerpc/atomic_arch.h @@ -1,15 +1,39 @@ -#define a_cas a_cas -static inline int a_cas(volatile int *p, int t, int s) -{ - __asm__("\n" - " sync\n" - "1: lwarx %0, 0, %4\n" - " cmpw %0, %2\n" - " bne 1f\n" - " stwcx. %3, 0, %4\n" - " bne- 1b\n" - " isync\n" - "1: \n" - : "=&r"(t), "+m"(*p) : "r"(t), "r"(s), "r"(p) : "cc", "memory" ); - return t; +#define a_ll a_ll +static inline int a_ll(volatile int *p) +{ + int v; + __asm__ __volatile__ ("lwarx %0, 0, %2" : "=r"(v) : "m"(*p), "r"(p)); + return v; +} + +#define a_sc a_sc +static inline int a_sc(volatile int *p, int v) +{ + int r; + __asm__ __volatile__ ( + "stwcx. %2, 0, %3 ; mfcr %0" + : "=r"(r), "=m"(*p) : "r"(v), "r"(p) : "memory", "cc"); + return r & 0x20000000; /* "bit 2" of "cr0" (backwards bit order) */ +} + +#define a_barrier a_barrier +static inline void a_barrier() +{ + __asm__ __volatile__ ("sync" : : : "memory"); +} + +#define a_pre_llsc a_barrier + +#define a_post_llsc a_post_llsc +static inline void a_post_llsc() +{ + __asm__ __volatile__ ("isync" : : : "memory"); +} + +#define a_store a_store +static inline void a_store(volatile int *p, int v) +{ + a_pre_llsc(); + *p = v; + a_post_llsc(); } |