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authorRich Felker <dalias@aerifal.cx>2016-01-20 02:07:59 +0000
committerRich Felker <dalias@aerifal.cx>2016-01-20 02:07:59 +0000
commitaf21a82ccc8687aa16e85def7db95efeae4cf72e (patch)
tree6b34bd5b507fe4076ce3c3f4556cad3d860a2a95 /src/fenv/arm
parent4b9a08f29303661e9680fc1ee1569daa25df7d50 (diff)
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switch arm, sh, and mips fenv asm from .sub system to .S files
Diffstat (limited to 'src/fenv/arm')
-rw-r--r--src/fenv/arm/fenv-hf.S69
-rw-r--r--src/fenv/arm/fenv.c3
2 files changed, 72 insertions, 0 deletions
diff --git a/src/fenv/arm/fenv-hf.S b/src/fenv/arm/fenv-hf.S
new file mode 100644
index 00000000..f55d798a
--- /dev/null
+++ b/src/fenv/arm/fenv-hf.S
@@ -0,0 +1,69 @@
+#if __ARM_PCS_VFP
+
+.syntax unified
+.fpu vfp
+
+.global fegetround
+.type fegetround,%function
+fegetround:
+ fmrx r0, fpscr
+ and r0, r0, #0xc00000
+ bx lr
+
+.global __fesetround
+.type __fesetround,%function
+__fesetround:
+ fmrx r3, fpscr
+ bic r3, r3, #0xc00000
+ orr r3, r3, r0
+ fmxr fpscr, r3
+ mov r0, #0
+ bx lr
+
+.global fetestexcept
+.type fetestexcept,%function
+fetestexcept:
+ and r0, r0, #0x1f
+ fmrx r3, fpscr
+ and r0, r0, r3
+ bx lr
+
+.global feclearexcept
+.type feclearexcept,%function
+feclearexcept:
+ and r0, r0, #0x1f
+ fmrx r3, fpscr
+ bic r3, r3, r0
+ fmxr fpscr, r3
+ mov r0, #0
+ bx lr
+
+.global feraiseexcept
+.type feraiseexcept,%function
+feraiseexcept:
+ and r0, r0, #0x1f
+ fmrx r3, fpscr
+ orr r3, r3, r0
+ fmxr fpscr, r3
+ mov r0, #0
+ bx lr
+
+.global fegetenv
+.type fegetenv,%function
+fegetenv:
+ fmrx r3, fpscr
+ str r3, [r0]
+ mov r0, #0
+ bx lr
+
+.global fesetenv
+.type fesetenv,%function
+fesetenv:
+ cmn r0, #1
+ moveq r3, #0
+ ldrne r3, [r0]
+ fmxr fpscr, r3
+ mov r0, #0
+ bx lr
+
+#endif
diff --git a/src/fenv/arm/fenv.c b/src/fenv/arm/fenv.c
new file mode 100644
index 00000000..ad295f58
--- /dev/null
+++ b/src/fenv/arm/fenv.c
@@ -0,0 +1,3 @@
+#if !__ARM_PCS_VFP
+#include "../fenv.c"
+#endif