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author | Rich Felker <dalias@aerifal.cx> | 2016-01-21 19:28:15 +0000 |
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committer | Rich Felker <dalias@aerifal.cx> | 2016-01-21 19:43:04 +0000 |
commit | 61b1e75f7d8004461f2e18f171c26c2f545eed32 (patch) | |
tree | 7a88f8d51ee3f049745b147b7f36fc8ee22e0e62 /src/thread/sh/__set_thread_area.c | |
parent | 1315596b510189b5159e742110b504177bdd4932 (diff) | |
download | musl-61b1e75f7d8004461f2e18f171c26c2f545eed32.tar.gz musl-61b1e75f7d8004461f2e18f171c26c2f545eed32.tar.bz2 musl-61b1e75f7d8004461f2e18f171c26c2f545eed32.tar.xz musl-61b1e75f7d8004461f2e18f171c26c2f545eed32.zip |
overhaul sh atomics for new atomics framework, add j-core cas.l backend
sh needs runtime-selected atomic backends since there are a number of
supported models that use non-forwards-compatible (non-smp-compatible)
atomic mechanisms. previously, the code paths for this were highly
inefficient since they involved C function calls with multiple
branches in the callee and heavy spills in the caller. the new code
performs calls the runtime-selected asm fragment from inline asm with
extremely minimal clobbers, rather than using a function call.
for the sh4a case where the atomic mechanism is known and there is no
forward-compatibility issue, the movli.l and movco.l instructions are
provided as a_ll and a_sc, allowing the new shared atomic.h to
generate efficient inline versions of all the basic atomic operations
without needing a cas loop.
Diffstat (limited to 'src/thread/sh/__set_thread_area.c')
-rw-r--r-- | src/thread/sh/__set_thread_area.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/thread/sh/__set_thread_area.c b/src/thread/sh/__set_thread_area.c new file mode 100644 index 00000000..9c47f78d --- /dev/null +++ b/src/thread/sh/__set_thread_area.c @@ -0,0 +1,40 @@ +#include "pthread_impl.h" +#include "libc.h" +#include <elf.h> + +/* Also perform sh-specific init */ + +#define CPU_HAS_LLSC 0x0040 +#define CPU_HAS_CAS_L 0x0400 + +__attribute__((__visibility__("hidden"))) +extern const char __sh_cas_gusa[], __sh_cas_llsc[], __sh_cas_imask[], __sh_cas_cas_l[]; + +__attribute__((__visibility__("hidden"))) +const void *__sh_cas_ptr; + +__attribute__((__visibility__("hidden"))) +unsigned __sh_nommu; + +int __set_thread_area(void *p) +{ + size_t *aux; + __asm__ __volatile__ ( "ldc %0, gbr" : : "r"(p) : "memory" ); +#ifndef __SH4A__ + __sh_cas_ptr = __sh_cas_gusa; +#if !defined(__SH3__) && !defined(__SH4__) + for (aux=libc.auxv; *aux; aux+=2) { + if (*aux != AT_PLATFORM) continue; + const char *s = (void *)aux[1]; + if (s[0]!='s' || s[1]!='h' || s[2]!='2' || s[3]-'0'<10u) break; + __sh_cas_ptr = __sh_cas_imask; + __sh_nommu = 1; + } +#endif + if (__hwcap & CPU_HAS_CAS_L) + __sh_cas_ptr = __sh_cas_cas_l; + else if (__hwcap & CPU_HAS_LLSC) + __sh_cas_ptr = __sh_cas_llsc; +#endif + return 0; +} |