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three ABIs are supported: the default with 68881 80-bit fpu format and
results returned in floating point registers, softfloat-only with the
same format, and coldfire fpu with IEEE single/double only. only the
first is tested at all, and only under qemu which has fpu emulation
bugs.
basic functionality smoke tests have been performed for the most
common arch-specific breakage via libc-test and qemu user-level
emulation. some sysvipc failures remain, but are shared with other big
endian archs and will be fixed separately.
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based on patch submitted by Jaydeep Patil, with minor changes.
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Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different
instruction set for floating point operations (SPE).
Executing regular PowerPC floating point instructions results in
"Illegal instruction" errors.
Make it possible to run these devices in soft-float mode.
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patch by Mahesh Bodapati and Jaydeep Patil of Imagination
Technologies.
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these files are all accepted as legacy arm syntax when producing arm
code, but legacy syntax cannot be used for producing thumb2 with
access to the full ISA. even after switching to UAL, some asm source
files contain instructions which are not valid in thumb mode, so these
will need to be addressed separately.
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mrc/mcr p10 coprocessor mnemonics are deprecated by some
toolchains.
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Some armhf gcc toolchains (built with --with-float=hard but without
--with-fpu=vfp*) do not pass -mfpu=vfp to the assembler and then
binutils rejects the UAL mnemonics for VFP unless there is an .fpu vfp
directive in the asm source.
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patch by Anand Takale.
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commit 5fc1487832e16aa2119e735a388d5f36c8c139e2 attempted to fix it,
but neglected the fact that mips has branch delay slots.
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This adds complete aarch64 target support including bigendian subarch.
Some of the long double math functions are known to be broken otherwise
interfaces should be fully functional, but at this point consider this
port experimental.
Initial work on this port was done by Sireesh Tripurari and Kevin Bortis.
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Implemented as a wrapper around fegetround introducing a new function
to the ABI: __flt_rounds. (fegetround cannot be used directly from float.h)
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armhf fesetenv implementation did a useless read of the fpscr.
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mips fesetenv did not handle FE_DFL_ENV, now fcsr is cleared in that
case.
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linux, gcc, etc. all use "sh" as the name for the superh arch. there
was already some inconsistency internally in musl: the dynamic linker
was searching for "ld-musl-sh.path" as its path file despite its own
name being "ld-musl-superh.so.1". there was some sentiment in both
directions as to how to resolve the inconsistency, but overall "sh"
was favored.
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the build system has no automatic way to know this code applies to
both big (default) and little endian variants, so explicit .sub files
are needed.
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Userspace emulated floating-point (gcc -msoft-float) is not compatible
with the default mips abi (assumes an FPU or in kernel emulation of it).
Soft vs hard float abi should not be mixed, __mips_soft_float is checked
in musl's configure script and there is no runtime check. The -sf subarch
does not save/restore floating-point registers in setjmp/longjmp and only
provides dummy fenv implementation.
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the default fenv was not set up properly, in particular the
tag word that indicates the contents of the x87 registers was
set to 0 (used) instead of 0xffff (empty)
this could cause random crashes after setting the default fenv
because it corrupted the fpu stack and then any float computation
gives NaN result breaking the program logic (usually after a
float to integer conversion).
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i386 fenv code checks __hwcap for sse support, but in fesetround the sse
code was unconditionally jumped over after the test so the sse rounding
mode was never set.
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there is no non-dot version of the andis instruction, but there's no
harm in updating the flags anyway, so just use the dot version.
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fesetround.c is a wrapper to do the arch independent argument
check (on archs where rounding mode is not stored in 2 bits
__fesetround still has to check its arguments)
on powerpc fe*except functions do not accept the extra invalid
flags of its fpscr register
the useless FENV_ACCESS pragma was removed from feupdateenv
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the x87 exception summary (ES) and stack fault (SF) flags may be
spuriously cleared by feclearexcept using the fnclex instruction,
but these flags are not observable through libc hence maintaining
their state is not critical.
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the sse and x87 rounding modes should be always the same,
the visible exception flags are the bitwise or of the two
fenv states (so it's enough to query the rounding mode or
raise exceptions on one fenv)
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patch by nsz. I've tested it on an armhf machine and it seems to be
working correctly.
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based on code sent to the mailing list by nsz, with minor changes.
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untested; may need followup-fixes.
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if all exception flags will be cleared, we can avoid the expensive
store/reload of the environment and just use the fnclex instruction.
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Note that the new fesetround has slightly different semantics:
Storing the floating-point environment with fnstenv makes the
next fldenv (or fldcw) "non-signaling", so unmasked and pending
exceptions does not invoke the exception handler.
(These are rare since exceptions are handled immediately and by
default all exceptions are masked anyway. But if one manually
unmasks an exception in the control word then either sets the
corresponding exception flag in the status word or the execution
of an exception raising floating-point operation gets interrupted
then it may happen).
So the old implementation did not trap in some rare cases
where the new implementation traps.
However POSIX does not specify anything like the x87 exception
handling traps and the fnstenv/fldenv pair is significantly slower
than the fnstcw/fldcw pair (new code is about 5x faster here and
it's dominated by the function call overhead).
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at present the i386 code does not support sse floating point, which is
not part of the standard i386 abi. while it may be desirable to
support it later, doing so will reduce performance and require some
tricks to probe if sse support is present.
this first commit is i386-only, but it should be trivial to port the
asm to x86_64.
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