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authorA. Wilcox <AWilcox@Wilcox-Tech.com>2018-07-29 22:42:38 -0500
committerA. Wilcox <AWilcox@Wilcox-Tech.com>2018-07-29 22:42:38 -0500
commit6f60664e8dd64ead7238452a515b1fa914e80793 (patch)
treea75d25ea17a5bbe439e0b06f0325484dc0a7a312 /user/qemu/ppc32-musl-support.patch
parent2552843d964162f7ba105775c05a231d9cdd4ae8 (diff)
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user/qemu: fix build on ppc
Diffstat (limited to 'user/qemu/ppc32-musl-support.patch')
-rw-r--r--user/qemu/ppc32-musl-support.patch16
1 files changed, 16 insertions, 0 deletions
diff --git a/user/qemu/ppc32-musl-support.patch b/user/qemu/ppc32-musl-support.patch
new file mode 100644
index 000000000..4c6ab59eb
--- /dev/null
+++ b/user/qemu/ppc32-musl-support.patch
@@ -0,0 +1,16 @@
+--- qemu-2.12.0/accel/tcg/user-exec.c.old 2018-07-30 03:20:04.910000000 +0000
++++ qemu-2.12.0/accel/tcg/user-exec.c 2018-07-30 03:38:57.350000000 +0000
+@@ -304,8 +304,13 @@
+ #define CR_sig(context) REG_sig(ccr, context)
+
+ #else // Musl
++#if defined(_ARCH_PPC64)
+ #define REG_sig(reg_num, context) \
+ ((context)->uc_mcontext.gp_regs[reg_num])
++#else
++#define REG_sig(reg_num, context) \
++ ((context)->uc_mcontext.gregs[reg_num])
++#endif
+ /* Gpr Registers access */
+ #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
+ /* Program counter */