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-rw-r--r--user/llvm6/APKBUILD12
-rw-r--r--user/llvm6/even-more-secure-plt.patch101
-rw-r--r--user/llvm6/more-secure-plt.patch38
-rw-r--r--user/llvm6/musl-ppc64-elfv2.patch52
-rw-r--r--user/llvm6/ppc32-calling-convention.patch69
5 files changed, 258 insertions, 14 deletions
diff --git a/user/llvm6/APKBUILD b/user/llvm6/APKBUILD
index f3bc9acc7..5f7b04fad 100644
--- a/user/llvm6/APKBUILD
+++ b/user/llvm6/APKBUILD
@@ -12,7 +12,7 @@ arch="all"
options="!checkroot !dbg"
url="https://llvm.org/"
license="NCSA"
-depends_dev="$pkgname=$pkgver-r$pkgrel"
+depends_dev="$pkgname=$pkgver-r$pkgrel libexecinfo-dev libxml2-dev"
makedepends="binutils-dev chrpath cmake file libexecinfo-dev libffi-dev
libxml2-dev python3 zlib-dev"
subpackages="$pkgname-static $pkgname-libs $pkgname-dev
@@ -24,6 +24,9 @@ source="http://llvm.org/releases/$pkgver/llvm-$pkgver.src.tar.xz
disable-dlclose-test.patch
musl-ppc64-elfv2.patch
secure-plt.patch
+ more-secure-plt.patch
+ even-more-secure-plt.patch
+ ppc32-calling-convention.patch
"
builddir="$srcdir/$_pkgname-$pkgver.src"
@@ -245,5 +248,8 @@ f84cd65d7042e89826ba6e8d48c4c302bf4980da369d7f19a55f217e51c00ca8ed178d453df3a3ce
6d1a716e5aa24e6b9a3acf4cc11e2504b1b01abf574074e9e5617b991de87d5e4e687eb18e85e73d5e632568afe2fc357771c4c96f9e136502071991496fb78c cmake-fix-libLLVM-name.patch
49c47f125014b60d0ea7870f981a2c1708ad705793f89287ed846ee881a837a4dc0170bf467e03f2ef56177473128945287749ac80dc2d13cfabcf8b929ba58a disable-FileSystemTest.CreateDir-perms-assert.patch
caeec8e4dbd92f5f74940780b69075f3879a267a8623822cbdc193fd14706eb089071e3a5a20d60cc2eca59e4c5b2a61d29827a2f3362ee7c5f74f11d9ace200 disable-dlclose-test.patch
-bde743960003a2a39868af9f665d86fadb0a7b1e7eb51c16ebbd74ce4c5220bbc400b1d5211c02fc2643863f49ee961e9a18dffa0eb813a0e1723613396512ab musl-ppc64-elfv2.patch
-35d289641fa4d200b5a3f62f1d51da600a734641356b0dc6c54a3080dd89aec3b031e36af8b53be49c35346c1cbcce00268de7ec9b4f552bfd7bf84d3504d1c4 secure-plt.patch"
+e5ddbc4b6c4928e79846dc3c022eb7928aaa8fed40515c78f5f03b8ab8264f34f1eb8aa8bfc0f436450932f4917e54ad261603032092ea271d9590f11a37cf1e musl-ppc64-elfv2.patch
+35d289641fa4d200b5a3f62f1d51da600a734641356b0dc6c54a3080dd89aec3b031e36af8b53be49c35346c1cbcce00268de7ec9b4f552bfd7bf84d3504d1c4 secure-plt.patch
+3d4a0a478bf800ea262c577451e22a1dbd5a4258226e49c66a697559263c8aa4fc0fff642a3c80ac3dfbb3efd6d9c0dbeb41dae1250fc7946de821cfef1ce1f0 more-secure-plt.patch
+deb71762721ebc73bfdf23143b582f40c70eddcef3e337ed14499e8e336bee2906292d38d64fe98fa633430c1bcb66cf6a2e067258c8fbe6e931f99f6d10a6f7 even-more-secure-plt.patch
+c3f596a1578a07ce0ee40c4e2576fe05ca6ca0c1b4f94b1f74c55cb09603afe7c846db9294fe28d83ca48633086bad422218e6d06e0d92173143fb298e06fb38 ppc32-calling-convention.patch"
diff --git a/user/llvm6/even-more-secure-plt.patch b/user/llvm6/even-more-secure-plt.patch
new file mode 100644
index 000000000..112e111b8
--- /dev/null
+++ b/user/llvm6/even-more-secure-plt.patch
@@ -0,0 +1,101 @@
+Index: lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
+===================================================================
+--- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
++++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
+@@ -442,13 +442,22 @@
+ // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
+ // come at the _end_ of the expression.
+ const MCOperand &Op = MI->getOperand(OpNo);
+- const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
+- O << refExp.getSymbol().getName();
++ const MCSymbolRefExpr *RefExp = nullptr;
++ const MCConstantExpr *ConstExp = nullptr;
++ if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
++ RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
++ ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
++ } else
++ RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
++
++ O << RefExp->getSymbol().getName();
+ O << '(';
+ printOperand(MI, OpNo+1, O);
+ O << ')';
+- if (refExp.getKind() != MCSymbolRefExpr::VK_None)
+- O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
++ if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
++ O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
++ if (ConstExp != nullptr)
++ O << '+' << ConstExp->getValue();
+ }
+
+ /// showRegistersWithPercentPrefix - Check if this register name should be
+Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
+===================================================================
+--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
++++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
+@@ -487,8 +487,14 @@
+ if (!Subtarget->isPPC64() && !Subtarget->isDarwin() &&
+ isPositionIndependent())
+ Kind = MCSymbolRefExpr::VK_PLT;
+- const MCSymbolRefExpr *TlsRef =
++ const MCExpr *TlsRef =
+ MCSymbolRefExpr::create(TlsGetAddr, Kind, OutContext);
++
++ // Add 32768 offset to the symbol so we follow up the latest GOT/PLT ABI.
++ if (Kind == MCSymbolRefExpr::VK_PLT && Subtarget->isSecurePlt())
++ TlsRef = MCBinaryExpr::createAdd(TlsRef,
++ MCConstantExpr::create(32768, OutContext),
++ OutContext);
+ const MachineOperand &MO = MI->getOperand(2);
+ const GlobalValue *GValue = MO.getGlobal();
+ MCSymbol *MOSymbol = getSymbol(GValue);
+Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+===================================================================
+--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
++++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+@@ -4054,7 +4054,20 @@
+ if (trySETCC(N))
+ return;
+ break;
+-
++ // These nodes will be transformed into GETtlsADDR32 node, which
++ // later becomes BL_TLS __tls_get_addr(sym at tlsgd)@PLT
++ case PPCISD::ADDI_TLSLD_L_ADDR:
++ case PPCISD::ADDI_TLSGD_L_ADDR: {
++ const Module *Mod = MF->getFunction().getParent();
++ if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) != MVT::i32 ||
++ !PPCSubTarget->isSecurePlt() || !PPCSubTarget->isTargetELF() ||
++ Mod->getPICLevel() == PICLevel::SmallPIC)
++ break;
++ // Attach global base pointer on GETtlsADDR32 node in order to
++ // generate secure plt code for TLS symbols.
++ getGlobalBaseReg();
++ }
++ break;
+ case PPCISD::CALL: {
+ const Module *M = MF->getFunction().getParent();
+
+Index: test/CodeGen/PowerPC/ppc32-secure-plt-tls.ll
+===================================================================
+--- a/test/CodeGen/PowerPC/ppc32-secure-plt-tls.ll
++++ b/test/CodeGen/PowerPC/ppc32-secure-plt-tls.ll
+@@ -0,0 +1,18 @@
++; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+secure-plt -relocation-model=pic | FileCheck -check-prefix=SECURE-PLT-TLS %s
++
++@a = thread_local local_unnamed_addr global i32 6, align 4
++define i32 @main() local_unnamed_addr #0 {
++entry:
++ %0 = load i32, i32* @a, align 4
++ ret i32 %0
++}
++
++
++!llvm.module.flags = !{!0}
++!0 = !{i32 7, !"PIC Level", i32 2}
++
++; SECURE-PLT-TLS: mflr 30
++; SECURE-PLT-TLS-NEXT: addis 30, 30, .LTOC-.L0$pb@ha
++; SECURE-PLT-TLS-NEXT: addi 30, 30, .LTOC-.L0$pb@l
++; SECURE-PLT-TLS-NEXT: bl .L{{.*}}
++; SECURE-PLT-TLS: bl __tls_get_addr(a@tlsgd)@PLT+32768
+\ No newline at end of file
diff --git a/user/llvm6/more-secure-plt.patch b/user/llvm6/more-secure-plt.patch
new file mode 100644
index 000000000..1cc08a9a8
--- /dev/null
+++ b/user/llvm6/more-secure-plt.patch
@@ -0,0 +1,38 @@
+diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
+index c0cbfd779cb..5d7a021c3e2 100644
+--- a/lib/Target/PowerPC/PPCSubtarget.cpp
++++ b/lib/Target/PowerPC/PPCSubtarget.cpp
+@@ -106,6 +106,7 @@
+ HasFloat128 = false;
+ IsISA3_0 = false;
+ UseLongCalls = false;
++ SecurePlt = false;
+
+ HasPOPCNTD = POPCNTD_Unavailable;
+ }
+@@ -136,6 +137,10 @@
+ if (isDarwin())
+ HasLazyResolverStubs = true;
+
++ // Set up musl-specific properties.
++ if (TargetTriple.getEnvironment() == Triple::Musl)
++ SecurePlt = true;
++
+ // QPX requires a 32-byte aligned stack. Note that we need to do this if
+ // we're compiling for a BG/Q system regardless of whether or not QPX
+ // is enabled because external functions will assume this alignment.
+diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
+index c583fba8cab..6a9eedf89c5 100644
+--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
++++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
+@@ -222,6 +222,10 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
+ if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)
+ return Reloc::PIC_;
+
++ // musl needs SecurePlt, which depends on PIC.
++ if (TT.getEnvironment() == Triple::Musl)
++ return Reloc::PIC_;
++
+ // 32-bit is static by default.
+ return Reloc::Static;
+ }
diff --git a/user/llvm6/musl-ppc64-elfv2.patch b/user/llvm6/musl-ppc64-elfv2.patch
index 6fa65526b..016be5dad 100644
--- a/user/llvm6/musl-ppc64-elfv2.patch
+++ b/user/llvm6/musl-ppc64-elfv2.patch
@@ -1,13 +1,43 @@
---- llvm-6.0.1.src/lib/Target/PowerPC/PPCTargetMachine.cpp.orig 2018-09-13 03:51:11.900000000 +0000
-+++ llvm-6.0.1.src/lib/Target/PowerPC/PPCTargetMachine.cpp 2018-09-13 03:56:10.740000000 +0000
-@@ -191,6 +191,10 @@
- if (TT.isMacOSX())
- return PPCTargetMachine::PPC_ABI_UNKNOWN;
-
-+ // musl uses ELFv2 ABI on both endians.
-+ if (TT.getEnvironment() == Triple::Musl)
-+ return PPCTargetMachine::PPC_ABI_ELFv2;
-+
- switch (TT.getArch()) {
+From 750d323a6060ad92c3d247f85d6555041f55b4a5 Mon Sep 17 00:00:00 2001
+From: "A. Wilcox" <AWilcox@Wilcox-Tech.com>
+Date: Thu, 4 Oct 2018 15:26:59 -0500
+Subject: [PATCH] Add support for powerpc64-*-linux-musl targets
+
+This patch ensures that 64-bit PowerPC musl targets use ELFv2 ABI on both
+endians. It additionally adds a test that big endian PPC64 uses ELFv2 on
+musl.
+---
+ lib/Target/PowerPC/PPCTargetMachine.cpp | 4 ++++
+ test/CodeGen/PowerPC/ppc64-elf-abi.ll | 1 +
+ 2 files changed, 5 insertions(+)
+
+diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
+index 34410393ef6..c583fba8cab 100644
+--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
++++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
+@@ -199,6 +199,10 @@ static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
case Triple::ppc64le:
return PPCTargetMachine::PPC_ABI_ELFv2;
+ case Triple::ppc64:
++ // musl uses ELFv2 ABI on both endians.
++ if (TT.getEnvironment() == Triple::Musl)
++ return PPCTargetMachine::PPC_ABI_ELFv2;
++
+ return PPCTargetMachine::PPC_ABI_ELFv1;
+ default:
+ return PPCTargetMachine::PPC_ABI_UNKNOWN;
+diff --git a/test/CodeGen/PowerPC/ppc64-elf-abi.ll b/test/CodeGen/PowerPC/ppc64-elf-abi.ll
+index 1e17930304b..aa594b37b47 100644
+--- a/test/CodeGen/PowerPC/ppc64-elf-abi.ll
++++ b/test/CodeGen/PowerPC/ppc64-elf-abi.ll
+@@ -1,6 +1,7 @@
+ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-ELFv1
+ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
+ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2
++; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-musl < %s | FileCheck %s -check-prefix=CHECK-ELFv2
+ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-ELFv2
+ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
+ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2
+--
+2.18.0
+
diff --git a/user/llvm6/ppc32-calling-convention.patch b/user/llvm6/ppc32-calling-convention.patch
new file mode 100644
index 000000000..2e6d66427
--- /dev/null
+++ b/user/llvm6/ppc32-calling-convention.patch
@@ -0,0 +1,69 @@
+Index: trunk/lib/Target/PowerPC/PPCISelLowering.cpp
+===================================================================
+--- trunk/lib/Target/PowerPC/PPCISelLowering.cpp
++++ trunk/lib/Target/PowerPC/PPCISelLowering.cpp
+@@ -3511,9 +3511,14 @@
+ // Argument stored in memory.
+ assert(VA.isMemLoc());
+
++ // Get the extended size of the argument type in stack
+ unsigned ArgSize = VA.getLocVT().getStoreSize();
+- int FI = MFI.CreateFixedObject(ArgSize, VA.getLocMemOffset(),
+- isImmutable);
++ // Get the actual size of the argument type
++ unsigned ObjSize = VA.getValVT().getStoreSize();
++ unsigned ArgOffset = VA.getLocMemOffset();
++ // Stack objects in PPC32 are right justified.
++ ArgOffset += ArgSize - ObjSize;
++ int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
+
+ // Create load nodes to retrieve arguments from the stack.
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+@@ -5468,10 +5473,15 @@
+ Arg = PtrOff;
+ }
+
+- if (VA.isRegLoc()) {
+- if (Arg.getValueType() == MVT::i1)
+- Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
++ // When useCRBits() is true, there can be i1 arguments.
++ // It is because getRegisterType(MVT::i1) => MVT::i1,
++ // and for other integer types getRegisterType() => MVT::i32.
++ // Extend i1 and ensure callee will get i32.
++ if (Arg.getValueType() == MVT::i1)
++ Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
++ dl, MVT::i32, Arg);
+
++ if (VA.isRegLoc()) {
+ seenFloatArg |= VA.getLocVT().isFloatingPoint();
+ // Put argument in a physical register.
+ RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
+Index: trunk/test/CodeGen/PowerPC/ppc32-i1-stack-arguments-abi-bug.ll
+===================================================================
+--- trunk/test/CodeGen/PowerPC/ppc32-i1-stack-arguments-abi-bug.ll
++++ trunk/test/CodeGen/PowerPC/ppc32-i1-stack-arguments-abi-bug.ll
+@@ -0,0 +1,24 @@
++; RUN: llc -verify-machineinstrs < %s -mcpu=ppc32 -mattr=+crbits | FileCheck %s
++target triple = "powerpc-unknown-linux-gnu"
++
++define void @check_callee(
++ i32, i32, i32, i32,
++ i32, i32, i32, i32,
++ i1 zeroext %s1
++) {
++ call void @check_caller(
++ i32 9, i32 9, i32 9, i32 9,
++ i32 9, i32 9, i32 9, i32 9,
++ i1 zeroext %s1)
++ ret void
++}
++
++; CHECK-LABEL: @check_callee
++; CHECK: lbz {{[0-9]+}}, 27(1)
++; CHECK: stw {{[0-9]+}}, 8(1)
++
++declare void @check_caller(
++ i32, i32, i32, i32,
++ i32, i32, i32, i32,
++ i1 zeroext
++)
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-02-25 11:16:03 +0000