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| author | Kevin Pedretti <ktpedre@sandia.gov> | 2021-10-11 16:55:45 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-10-12 00:55:45 +0200 |
| commit | 0b62974160d99c44e77366cac4bd2e8a1983505b (patch) | |
| tree | 0964d1a12fcf8c940bf03bdb2b98eb7cd93dd348 | |
| parent | 833f1de24ac7541c69991189c358079ef3d62046 (diff) | |
| download | spack-0b62974160d99c44e77366cac4bd2e8a1983505b.tar.gz spack-0b62974160d99c44e77366cac4bd2e8a1983505b.tar.bz2 spack-0b62974160d99c44e77366cac4bd2e8a1983505b.tar.xz spack-0b62974160d99c44e77366cac4bd2e8a1983505b.zip | |
openblas: fix build on riscv64 (#26565)
OpenBLAS now has support for the riscv64 architecture. This commit
extends the spack openblas package.py to handle building on riscv64.
| -rw-r--r-- | var/spack/repos/builtin/packages/openblas/package.py | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/var/spack/repos/builtin/packages/openblas/package.py b/var/spack/repos/builtin/packages/openblas/package.py index 1785b5105d..0c267eb931 100644 --- a/var/spack/repos/builtin/packages/openblas/package.py +++ b/var/spack/repos/builtin/packages/openblas/package.py @@ -191,7 +191,7 @@ class Openblas(MakefilePackage): # List of available architectures, and possible aliases openblas_arch = set(['alpha', 'arm', 'ia64', 'mips', 'mips64', - 'power', 'sparc', 'zarch']) + 'power', 'riscv64', 'sparc', 'zarch']) openblas_arch_map = { 'amd64': 'x86_64', 'powerpc64': 'power', @@ -220,7 +220,7 @@ class Openblas(MakefilePackage): arch_name = openblas_arch_map.get(arch_name, arch_name) args.append('ARCH=' + arch_name) - if microarch.vendor == 'generic': + if microarch.vendor == 'generic' and microarch.name != 'riscv64': # User requested a generic platform, or we couldn't find a good # match for the requested one. Allow OpenBLAS to determine # an optimized kernel at run time, including older CPUs, while @@ -238,6 +238,14 @@ class Openblas(MakefilePackage): if microarch.name == "skylake": # Special case for disabling avx512 instructions args.append('NO_AVX512=1') + + elif microarch.name == 'riscv64': + # Special case for renaming the generic riscv64 uarch to the + # corresponding OpenBLAS target. riscv64 does not yet support + # DYNAMIC_ARCH or TARGET=GENERIC. Once it does, this special + # case can go away. + args.append('TARGET=' + "RISCV64_GENERIC") + else: args.append('TARGET=' + microarch.name.upper()) |