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authorRich Felker <dalias@aerifal.cx>2014-07-19 13:43:46 -0400
committerRich Felker <dalias@aerifal.cx>2014-07-19 13:43:46 -0400
commitbb3a3befeaa01531c273ef9130f3fbcaaf8a25e2 (patch)
treeffca27de35e6eb9246b29ae792253e4931afe04e
parent94252dd341a7c72b31db2614abdc74142ad80562 (diff)
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fix build breakage from ppc asm constraints change
due to a mistake in my testing procedure, the changes in the previous commit were not correctly tested and wrongly assumed to be valid. the lwarx and stwcx. instructions do not accept general ppc memory address expressions and thus the argument associated with the memory constraint cannot be used directly. instead, the memory constraint can be left as an argument that the asm does not actually use, and the address can be provided in a separate register constraint.
-rw-r--r--arch/powerpc/atomic.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/atomic.h b/arch/powerpc/atomic.h
index 05951a2d..a1049bdb 100644
--- a/arch/powerpc/atomic.h
+++ b/arch/powerpc/atomic.h
@@ -25,13 +25,13 @@ static inline int a_ctz_64(uint64_t x)
static inline int a_cas(volatile int *p, int t, int s)
{
- __asm__("1: lwarx %0, 0, %1\n"
+ __asm__("1: lwarx %0, 0, %4\n"
" cmpw %0, %2\n"
" bne 1f\n"
- " stwcx. %3, 0, %1\n"
+ " stwcx. %3, 0, %4\n"
" bne- 1b\n"
"1: \n"
- : "=&r"(t), "+m"(*p) : "r"(t), "r"(s) : "cc", "memory" );
+ : "=&r"(t), "+m"(*p) : "r"(t), "r"(s), "r"(p) : "cc", "memory" );
return t;
}