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authorRich Felker <dalias@aerifal.cx>2015-04-17 22:19:01 -0400
committerRich Felker <dalias@aerifal.cx>2015-04-17 22:19:01 -0400
commitaecdbb3042704075b303b626da424aa0665e4f97 (patch)
tree5eac6f13b1da36bf5d7cbcadfb91a85151c43694 /src/aio
parent33615cd5ca4d40286d3000a941f96c5bebdf39fb (diff)
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fix PLT call offset in sh dlsym asm
the braf instruction's destination register is an offset from the address of the braf instruction plus 4 (or equivalently, the address of the next instruction after the delay slot). the code for dlsym was incorrectly computing the offset to pass using the address of the delay slot itself. in other places, a label was placed after the delay slot, but I find this confusing. putting the label on the branch instruction itself, and manually adding 4, makes it more clear which branch the offset in the constant pool goes with.
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