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author | Rich Felker <dalias@aerifal.cx> | 2018-06-14 14:26:30 -0400 |
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committer | Rich Felker <dalias@aerifal.cx> | 2018-06-19 13:24:05 -0400 |
commit | f81e44a0d96c88e052e51982f9fdd6fe0a212b46 (patch) | |
tree | e8a21317b5af5a2d09543ffcb0fbf1f0a668b63a /src/fenv/m68k/fenv.c | |
parent | 18f02c42a2b5397e8541f4663eb6ca00c1a806dd (diff) | |
download | musl-f81e44a0d96c88e052e51982f9fdd6fe0a212b46.tar.gz musl-f81e44a0d96c88e052e51982f9fdd6fe0a212b46.tar.bz2 musl-f81e44a0d96c88e052e51982f9fdd6fe0a212b46.tar.xz musl-f81e44a0d96c88e052e51982f9fdd6fe0a212b46.zip |
add m68k port
three ABIs are supported: the default with 68881 80-bit fpu format and
results returned in floating point registers, softfloat-only with the
same format, and coldfire fpu with IEEE single/double only. only the
first is tested at all, and only under qemu which has fpu emulation
bugs.
basic functionality smoke tests have been performed for the most
common arch-specific breakage via libc-test and qemu user-level
emulation. some sysvipc failures remain, but are shared with other big
endian archs and will be fixed separately.
Diffstat (limited to 'src/fenv/m68k/fenv.c')
-rw-r--r-- | src/fenv/m68k/fenv.c | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/src/fenv/m68k/fenv.c b/src/fenv/m68k/fenv.c new file mode 100644 index 00000000..e60949d1 --- /dev/null +++ b/src/fenv/m68k/fenv.c @@ -0,0 +1,84 @@ +#include <fenv.h> + +#if __HAVE_68881__ || __mcffpu__ + +static unsigned getsr() +{ + unsigned v; + __asm__ __volatile__ ("fmove.l %%fpsr,%0" : "=dm"(v)); + return v; +} + +static void setsr(unsigned v) +{ + __asm__ __volatile__ ("fmove.l %0,%%fpsr" : : "dm"(v)); +} + +static unsigned getcr() +{ + unsigned v; + __asm__ __volatile__ ("fmove.l %%fpcr,%0" : "=dm"(v)); + return v; +} + +static void setcr(unsigned v) +{ + __asm__ __volatile__ ("fmove.l %0,%%fpcr" : : "dm"(v)); +} + +int feclearexcept(int mask) +{ + if (mask & ~FE_ALL_EXCEPT) return -1; + setsr(getsr() & ~mask); + return 0; +} + +int feraiseexcept(int mask) +{ + if (mask & ~FE_ALL_EXCEPT) return -1; + setsr(getsr() | mask); + return 0; +} + +int fetestexcept(int mask) +{ + return getsr() & mask; +} + +int fegetround(void) +{ + return getcr() & FE_UPWARD; +} + +int __fesetround(int r) +{ + setcr((getcr() & ~FE_UPWARD) | r); + return 0; +} + +int fegetenv(fenv_t *envp) +{ + envp->__control_register = getcr(); + envp->__status_register = getsr(); + __asm__ __volatile__ ("fmove.l %%fpiar,%0" + : "=dm"(envp->__instruction_address)); + return 0; +} + +int fesetenv(const fenv_t *envp) +{ + static const fenv_t default_env = { 0 }; + if (envp == FE_DFL_ENV) + envp = &default_env; + setcr(envp->__control_register); + setsr(envp->__status_register); + __asm__ __volatile__ ("fmove.l %0,%%fpiar" + : : "dm"(envp->__instruction_address)); + return 0; +} + +#else + +#include "../fenv.c" + +#endif |