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author | Felix Fietkau <nbd@openwrt.org> | 2016-01-25 13:20:52 +0100 |
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committer | Rich Felker <dalias@aerifal.cx> | 2016-03-06 17:03:01 -0500 |
commit | 5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb (patch) | |
tree | a7a12a71e2a505ed4a5c20c1356fc2d7cf2cb2f1 /src/setjmp/powerpc/longjmp.S | |
parent | 9543656cc32fda48fc463f332ee20e91eed2b768 (diff) | |
download | musl-5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb.tar.gz musl-5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb.tar.bz2 musl-5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb.tar.xz musl-5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb.zip |
add powerpc soft-float support
Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different
instruction set for floating point operations (SPE).
Executing regular PowerPC floating point instructions results in
"Illegal instruction" errors.
Make it possible to run these devices in soft-float mode.
Diffstat (limited to 'src/setjmp/powerpc/longjmp.S')
-rw-r--r-- | src/setjmp/powerpc/longjmp.S | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/src/setjmp/powerpc/longjmp.S b/src/setjmp/powerpc/longjmp.S new file mode 100644 index 00000000..e598bd05 --- /dev/null +++ b/src/setjmp/powerpc/longjmp.S @@ -0,0 +1,69 @@ + .global _longjmp + .global longjmp + .type _longjmp,@function + .type longjmp,@function +_longjmp: +longjmp: + /* + * void longjmp(jmp_buf env, int val); + * put val into return register and restore the env saved in setjmp + * if val(r4) is 0, put 1 there. + */ + /* 0) move old return address into r0 */ + lwz 0, 0(3) + /* 1) put it into link reg */ + mtlr 0 + /* 2 ) restore stack ptr */ + lwz 1, 4(3) + /* 3) restore control reg */ + lwz 0, 8(3) + mtcr 0 + /* 4) restore r14-r31 */ + lwz 14, 12(3) + lwz 15, 16(3) + lwz 16, 20(3) + lwz 17, 24(3) + lwz 18, 28(3) + lwz 19, 32(3) + lwz 20, 36(3) + lwz 21, 40(3) + lwz 22, 44(3) + lwz 23, 48(3) + lwz 24, 52(3) + lwz 25, 56(3) + lwz 26, 60(3) + lwz 27, 64(3) + lwz 28, 68(3) + lwz 29, 72(3) + lwz 30, 76(3) + lwz 31, 80(3) +#ifndef _SOFT_FLOAT + lfd 14,88(3) + lfd 15,96(3) + lfd 16,104(3) + lfd 17,112(3) + lfd 18,120(3) + lfd 19,128(3) + lfd 20,136(3) + lfd 21,144(3) + lfd 22,152(3) + lfd 23,160(3) + lfd 24,168(3) + lfd 25,176(3) + lfd 26,184(3) + lfd 27,192(3) + lfd 28,200(3) + lfd 29,208(3) + lfd 30,216(3) + lfd 31,224(3) +#endif + /* 5) put val into return reg r3 */ + mr 3, 4 + + /* 6) check if return value is 0, make it 1 in that case */ + cmpwi cr7, 4, 0 + bne cr7, 1f + li 3, 1 +1: + blr + |