1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
|
#ifndef _INTERNAL_ATOMIC_H
#define _INTERNAL_ATOMIC_H
#include <stdint.h>
static inline int a_ctz_64(uint64_t x)
{
__asm__(
" rbit %0, %1\n"
" clz %0, %0\n"
: "=r"(x) : "r"(x));
return x;
}
static inline int a_ctz_l(unsigned long x)
{
return a_ctz_64(x);
}
static inline void a_barrier()
{
__asm__ __volatile__("dmb ish");
}
static inline void *a_cas_p(volatile void *p, void *t, void *s)
{
void *old;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %0,%3\n"
" cmp %0,%1\n"
" b.ne 1f\n"
" stxr %w0,%2,%3\n"
" cbnz %w0,1b\n"
" mov %0,%1\n"
"1: dmb ish\n"
: "=&r"(old)
: "r"(t), "r"(s), "Q"(*(long*)p)
: "memory", "cc");
return old;
}
static inline int a_cas(volatile int *p, int t, int s)
{
int old;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %w0,%3\n"
" cmp %w0,%w1\n"
" b.ne 1f\n"
" stxr %w0,%w2,%3\n"
" cbnz %w0,1b\n"
" mov %w0,%w1\n"
"1: dmb ish\n"
: "=&r"(old)
: "r"(t), "r"(s), "Q"(*p)
: "memory", "cc");
return old;
}
static inline int a_swap(volatile int *x, int v)
{
int old, tmp;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %w0,%3\n"
" stxr %w1,%w2,%3\n"
" cbnz %w1,1b\n"
" dmb ish\n"
: "=&r"(old), "=&r"(tmp)
: "r"(v), "Q"(*x)
: "memory", "cc" );
return old;
}
static inline int a_fetch_add(volatile int *x, int v)
{
int old, tmp;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %w0,%3\n"
" add %w0,%w0,%w2\n"
" stxr %w1,%w0,%3\n"
" cbnz %w1,1b\n"
" dmb ish\n"
: "=&r"(old), "=&r"(tmp)
: "r"(v), "Q"(*x)
: "memory", "cc" );
return old-v;
}
static inline void a_inc(volatile int *x)
{
int tmp, tmp2;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %w0,%2\n"
" add %w0,%w0,#1\n"
" stxr %w1,%w0,%2\n"
" cbnz %w1,1b\n"
" dmb ish\n"
: "=&r"(tmp), "=&r"(tmp2)
: "Q"(*x)
: "memory", "cc" );
}
static inline void a_dec(volatile int *x)
{
int tmp, tmp2;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %w0,%2\n"
" sub %w0,%w0,#1\n"
" stxr %w1,%w0,%2\n"
" cbnz %w1,1b\n"
" dmb ish\n"
: "=&r"(tmp), "=&r"(tmp2)
: "Q"(*x)
: "memory", "cc" );
}
static inline void a_and_64(volatile uint64_t *p, uint64_t v)
{
int tmp, tmp2;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %0,%3\n"
" and %0,%0,%2\n"
" stxr %w1,%0,%3\n"
" cbnz %w1,1b\n"
" dmb ish\n"
: "=&r"(tmp), "=&r"(tmp2)
: "r"(v), "Q"(*p)
: "memory", "cc" );
}
static inline void a_and(volatile int *p, int v)
{
int tmp, tmp2;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %w0,%3\n"
" and %w0,%w0,%w2\n"
" stxr %w1,%w0,%3\n"
" cbnz %w1,1b\n"
" dmb ish\n"
: "=&r"(tmp), "=&r"(tmp2)
: "r"(v), "Q"(*p)
: "memory", "cc" );
}
static inline void a_or_64(volatile uint64_t *p, uint64_t v)
{
int tmp, tmp2;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %0,%3\n"
" orr %0,%0,%2\n"
" stxr %w1,%0,%3\n"
" cbnz %w1,1b\n"
" dmb ish\n"
: "=&r"(tmp), "=&r"(tmp2)
: "r"(v), "Q"(*p)
: "memory", "cc" );
}
static inline void a_or_l(volatile void *p, long v)
{
return a_or_64(p, v);
}
static inline void a_or(volatile int *p, int v)
{
int tmp, tmp2;
__asm__ __volatile__(
" dmb ish\n"
"1: ldxr %w0,%3\n"
" orr %w0,%w0,%w2\n"
" stxr %w1,%w0,%3\n"
" cbnz %w1,1b\n"
" dmb ish\n"
: "=&r"(tmp), "=&r"(tmp2)
: "r"(v), "Q"(*p)
: "memory", "cc" );
}
static inline void a_store(volatile int *p, int x)
{
__asm__ __volatile__(
" dmb ish\n"
" str %w1,%0\n"
" dmb ish\n"
: "=m"(*p)
: "r"(x)
: "memory", "cc" );
}
#define a_spin a_barrier
static inline void a_crash()
{
*(volatile char *)0=0;
}
#endif
|
