user/llvm8: Additional powerpc fixes

Two bugs found by running the rust 1.37.0 test suite:
- Use the PIC sequence for getting the GOT address when resolving IE TLS
  in a PIE. The non-PIC code sequence creates bogus dynamic relocations.
- Only use the PLT in PIC mode. Otherwise, calls to a DSO from a non-PIE
  dynamic executable force bss-plt, since secure-plt requires PIC.

Signed-off-by: Samuel Holland <samuel@sholland.org>

2 files changed, 142 insertions, 25 deletions

diff --git a/user/llvm8/APKBUILD b/user/llvm8/APKBUILD
index 6913646a3..0e09db7af 100644
--- a/user/llvm8/APKBUILD
+++ b/user/llvm8/APKBUILD
@@ -109,7 +109,7 @@ build() {
 check() {
 	# appears to be an issue on musl and glibc, but only fails on musl:
 	# https://github.com/NixOS/nixpkgs/blob/bb7e9e46/pkgs/development/compilers/llvm/8/llvm.nix#L74
-	rm "$builddir"/test/CodeGen/AArch64/wineh4.mir
+	rm -f "$builddir"/test/CodeGen/AArch64/wineh4.mir
 	make -C build check-llvm
 }
 
@@ -231,6 +231,6 @@ f84cd65d7042e89826ba6e8d48c4c302bf4980da369d7f19a55f217e51c00ca8ed178d453df3a3ce
 49c47f125014b60d0ea7870f981a2c1708ad705793f89287ed846ee881a837a4dc0170bf467e03f2ef56177473128945287749ac80dc2d13cfabcf8b929ba58a  disable-FileSystemTest.CreateDir-perms-assert.patch
 caeec8e4dbd92f5f74940780b69075f3879a267a8623822cbdc193fd14706eb089071e3a5a20d60cc2eca59e4c5b2a61d29827a2f3362ee7c5f74f11d9ace200  disable-dlclose-test.patch
 e5ddbc4b6c4928e79846dc3c022eb7928aaa8fed40515c78f5f03b8ab8264f34f1eb8aa8bfc0f436450932f4917e54ad261603032092ea271d9590f11a37cf1e  musl-ppc64-elfv2.patch
-957516510439be661ad04e061e9616da8a271a5621603238cde5b4782bd2465367eaaa5ade628d163c8d9e70b8b0495687669f4648bd031ac6e5a1582d2e75a4  more-secure-plt.patch
+7ba7f5b396e1afb49ea53fdc16729f0709fbba88de433cc8a8e2f751d13733011d4121318f68d7f8a16a6c57c3a1bee727cc3e0da0f5c6cae38eff70d3a539cf  more-secure-plt.patch
 deb71762721ebc73bfdf23143b582f40c70eddcef3e337ed14499e8e336bee2906292d38d64fe98fa633430c1bcb66cf6a2e067258c8fbe6e931f99f6d10a6f7  even-more-secure-plt.patch
 53cc0d13dd871e9b775bb4e7567de4f9a97d91b8246cd7ce74607fd88d6e3e2ab9455f5b4195bc7f9dbdedbc77d659d43e98ec0b7cd78cd395aaea6919510287  python3-test.patch"
diff --git a/user/llvm8/more-secure-plt.patch b/user/llvm8/more-secure-plt.patch
index 6728e2765..8b18a6db2 100644
--- a/user/llvm8/more-secure-plt.patch
+++ b/user/llvm8/more-secure-plt.patch
@@ -1,28 +1,145 @@
---- a/lib/Target/PowerPC/PPCSubtarget.cpp
-+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
-@@ -138,6 +138,10 @@
+--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
++++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+@@ -2769,8 +2769,12 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
+       SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
+       GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
+                            PtrVT, GOTReg, TGA);
+-    } else
+-      GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
++    } else {
++      if (isPositionIndependent())
++        GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
++      else
++        GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
++    }
+     SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
+                                    PtrVT, TGA, GOTPtr);
+     return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
+@@ -4941,7 +4945,8 @@ PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain,
+   if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee))
+     GV = G->getGlobal();
+   bool Local = TM.shouldAssumeDSOLocal(*Mod, GV);
+-  bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64;
++  bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64 &&
++                TM.isPositionIndependent();
+ 
+   if (isFunctionGlobalAddress(Callee)) {
+     GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
+--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
++++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+@@ -138,7 +138,8 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
    if (isDarwin())
      HasLazyResolverStubs = true;
-
-+  // Set up musl-specific properties.
-+  if (TargetTriple.getEnvironment() == Triple::Musl)
-+    SecurePlt = true;
-+
+ 
+-  if (TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD())
++  if (TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
++      TargetTriple.isMusl())
+     SecurePlt = true;
+ 
    if (HasSPE && IsPPC64)
-     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
-   if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))
-diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
-index c583fba8cab..6a9eedf89c5 100644
---- a/lib/Target/PowerPC/PPCTargetMachine.cpp
-+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
-@@ -222,6 +222,10 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT,
-   if (TT.getArch() == Triple::ppc64)
-     return Reloc::PIC_;
+--- llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
++++ llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
+@@ -62,7 +62,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
+ ; CHECK-NEXT:    lfd 4, 328(1)
+ ; CHECK-NEXT:    fmr 1, 31
+ ; CHECK-NEXT:    fmr 2, 30
+-; CHECK-NEXT:    bl __gcc_qmul@PLT
++; CHECK-NEXT:    bl __gcc_qmul
+ ; CHECK-NEXT:    lis 3, 16864
+ ; CHECK-NEXT:    stfd 1, 280(1)
+ ; CHECK-NEXT:    fmr 29, 1
+@@ -84,7 +84,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
+ ; CHECK-NEXT:    lfd 4, 360(1)
+ ; CHECK-NEXT:    lfd 1, 352(1)
+ ; CHECK-NEXT:    lfd 2, 344(1)
+-; CHECK-NEXT:    bl __gcc_qsub@PLT
++; CHECK-NEXT:    bl __gcc_qsub
+ ; CHECK-NEXT:    mffs 0
+ ; CHECK-NEXT:    mtfsb1 31
+ ; CHECK-NEXT:    lis 3, .LCPI0_1@ha
+@@ -117,7 +117,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
+ ; CHECK-NEXT:  .LBB0_5: # %bb1
+ ; CHECK-NEXT:    li 4, 0
+ ; CHECK-NEXT:    mr 3, 30
+-; CHECK-NEXT:    bl __floatditf@PLT
++; CHECK-NEXT:    bl __floatditf
+ ; CHECK-NEXT:    lis 3, 17392
+ ; CHECK-NEXT:    stfd 1, 208(1)
+ ; CHECK-NEXT:    fmr 29, 1
+@@ -140,7 +140,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
+ ; CHECK-NEXT:    lfd 4, 232(1)
+ ; CHECK-NEXT:    lfd 1, 224(1)
+ ; CHECK-NEXT:    lfd 2, 216(1)
+-; CHECK-NEXT:    bl __gcc_qadd@PLT
++; CHECK-NEXT:    bl __gcc_qadd
+ ; CHECK-NEXT:    blt 2, .LBB0_7
+ ; CHECK-NEXT:  # %bb.6: # %bb1
+ ; CHECK-NEXT:    fmr 2, 28
+@@ -163,7 +163,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
+ ; CHECK-NEXT:    stw 3, 248(1)
+ ; CHECK-NEXT:    lfd 3, 256(1)
+ ; CHECK-NEXT:    lfd 4, 248(1)
+-; CHECK-NEXT:    bl __gcc_qsub@PLT
++; CHECK-NEXT:    bl __gcc_qsub
+ ; CHECK-NEXT:    stfd 2, 176(1)
+ ; CHECK-NEXT:    fcmpu 0, 2, 27
+ ; CHECK-NEXT:    stfd 1, 168(1)
+@@ -205,7 +205,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
+ ; CHECK-NEXT:    lfd 4, 72(1)
+ ; CHECK-NEXT:    lfd 1, 64(1)
+ ; CHECK-NEXT:    lfd 2, 56(1)
+-; CHECK-NEXT:    bl __gcc_qsub@PLT
++; CHECK-NEXT:    bl __gcc_qsub
+ ; CHECK-NEXT:    mffs 0
+ ; CHECK-NEXT:    mtfsb1 31
+ ; CHECK-NEXT:    lis 3, .LCPI0_2@ha
+@@ -260,7 +260,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
+ ; CHECK-NEXT:    lfd 4, 136(1)
+ ; CHECK-NEXT:    lfd 1, 128(1)
+ ; CHECK-NEXT:    lfd 2, 120(1)
+-; CHECK-NEXT:    bl __gcc_qsub@PLT
++; CHECK-NEXT:    bl __gcc_qsub
+ ; CHECK-NEXT:    mffs 0
+ ; CHECK-NEXT:    mtfsb1 31
+ ; CHECK-NEXT:    lis 3, .LCPI0_0@ha
+--- llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
++++ llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+@@ -11,7 +11,7 @@ entry:
+ ; CHECK-DAG: ori [[T2:[0-9]+]], [[T2]], 34492
+ ; CHECK-DAG: stwx [[T1]], 1, [[T2]]
+ ; CHECK-DAG: addi 3, 1, 28
+-; CHECK: bl bar@PLT
++; CHECK: bl bar
+   %x = alloca [100000 x i8]                       ; <[100000 x i8]*> [#uses=1]
+   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+   %x1 = bitcast [100000 x i8]* %x to i8*          ; <i8*> [#uses=1]
+--- llvm/test/CodeGen/PowerPC/available-externally.ll
++++ llvm/test/CodeGen/PowerPC/available-externally.ll
+@@ -14,7 +14,7 @@ target triple = "powerpc-unknown-linux-gnu"
+ define i32 @foo(i64 %x) nounwind {
+ entry:
+ ; STATIC: foo:
+-; STATIC: bl exact_log2@PLT
++; STATIC: bl exact_log2
+ ; STATIC: blr
  
-+  // musl needs SecurePlt, which depends on PIC.
-+  if (TT.getEnvironment() == Triple::Musl)
-+    return Reloc::PIC_;
-+
-   // Rest are static by default.
-   return Reloc::Static;
+ ; PIC: foo:
+--- llvm/test/CodeGen/PowerPC/stubs.ll
++++ llvm/test/CodeGen/PowerPC/stubs.ll
+@@ -6,4 +6,4 @@ entry:
  }
+ 
+ ; CHECK: test1:
+-; CHECK: bl __floatditf@PLT
++; CHECK: bl __floatditf
+--- llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
++++ llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
+@@ -72,7 +72,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
+ ; PPC32-NEXT: mr 28, 9
+ ; PPC32-NEXT: mr 23, 6
+ ; PPC32-NEXT: mr 24, 5
+-; PPC32-NEXT: bl __multi3@PLT
++; PPC32-NEXT: bl __multi3
+ ; PPC32-NEXT: mr 7, 4
+ ; PPC32-NEXT: mullw 4, 24, 30
+ ; PPC32-NEXT: mullw 8, 29, 23