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| author | Chris Green <greenc@fnal.gov> | 2019-10-24 12:44:58 -0500 |
|---|---|---|
| committer | Greg Becker <becker33@llnl.gov> | 2019-10-24 12:44:58 -0500 |
| commit | 09133288128a4968bf211b603883dae7a23fac6a (patch) | |
| tree | 38af130d9aa6b7814b3009d5a3e74ede89a11f9f | |
| parent | f65f2450df583702b3305ad5fe9ae1d72a7588be (diff) | |
| download | spack-09133288128a4968bf211b603883dae7a23fac6a.tar.gz spack-09133288128a4968bf211b603883dae7a23fac6a.tar.bz2 spack-09133288128a4968bf211b603883dae7a23fac6a.tar.xz spack-09133288128a4968bf211b603883dae7a23fac6a.zip | |
Correctly identify Skylake CPUs on Darwin. (#13377)
* Correctly identify Skylake CPUs on Darwin.
* Add a test for haswell on Mojave.
| -rw-r--r-- | lib/spack/llnl/util/cpu/detect.py | 4 | ||||
| -rw-r--r-- | lib/spack/spack/test/data/targets/darwin-mojave-haswell | 5 | ||||
| -rw-r--r-- | lib/spack/spack/test/data/targets/darwin-mojave-skylake (renamed from lib/spack/spack/test/data/targets/darwin-mojave-broadwell) | 0 | ||||
| -rw-r--r-- | lib/spack/spack/test/llnl/util/cpu.py | 4 |
4 files changed, 12 insertions, 1 deletions
diff --git a/lib/spack/llnl/util/cpu/detect.py b/lib/spack/llnl/util/cpu/detect.py index 92b75e9653..c89f67c852 100644 --- a/lib/spack/llnl/util/cpu/detect.py +++ b/lib/spack/llnl/util/cpu/detect.py @@ -117,6 +117,10 @@ def sysctl_info_dict(): info['flags'] += ' sse4_2' if 'avx1.0' in info['flags']: info['flags'] += ' avx' + if 'clfsopt' in info['flags']: + info['flags'] += ' clflushopt' + if 'xsave' in info['flags']: + info['flags'] += ' xsavec xsaveopt' return info diff --git a/lib/spack/spack/test/data/targets/darwin-mojave-haswell b/lib/spack/spack/test/data/targets/darwin-mojave-haswell new file mode 100644 index 0000000000..45054c5676 --- /dev/null +++ b/lib/spack/spack/test/data/targets/darwin-mojave-haswell @@ -0,0 +1,5 @@ +machdep.cpu.vendor: GenuineIntel +machdep.cpu.model: 70 +machdep.cpu.brand_string: Intel(R) Core(TM) i7-4980HQ CPU @ 2.80GHz +machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH DS ACPI MMX FXSR SSE SSE2 SS HTT TM PBE SSE3 PCLMULQDQ DTES64 MON DSCPL VMX SMX EST TM2 SSSE3 FMA CX16 TPR PDCM SSE4.1 SSE4.2 x2APIC MOVBE POPCNT AES PCID XSAVE OSXSAVE SEGLIM64 TSCTMR AVX1.0 RDRAND F16C +machdep.cpu.leaf7_features: RDWRFSGS TSC_THREAD_OFFSET BMI1 AVX2 SMEP BMI2 ERMS INVPCID FPU_CSDS MDCLEAR IBRS STIBP L1DF SSBD diff --git a/lib/spack/spack/test/data/targets/darwin-mojave-broadwell b/lib/spack/spack/test/data/targets/darwin-mojave-skylake index 67dc28a966..67dc28a966 100644 --- a/lib/spack/spack/test/data/targets/darwin-mojave-broadwell +++ b/lib/spack/spack/test/data/targets/darwin-mojave-skylake diff --git a/lib/spack/spack/test/llnl/util/cpu.py b/lib/spack/spack/test/llnl/util/cpu.py index 2e03772d19..7e32dda71a 100644 --- a/lib/spack/spack/test/llnl/util/cpu.py +++ b/lib/spack/spack/test/llnl/util/cpu.py @@ -29,7 +29,8 @@ from llnl.util.cpu import Microarchitecture # noqa 'linux-rhel6-piledriver', 'linux-centos7-power8le', 'darwin-mojave-ivybridge', - 'darwin-mojave-broadwell', + 'darwin-mojave-haswell', + 'darwin-mojave-skylake', 'bgq-rhel6-power7' ]) def expected_target(request, monkeypatch): @@ -156,6 +157,7 @@ def test_architecture_family(target_name, expected_family): ('skylake', 'sse3'), ('power8', 'altivec'), ('broadwell', 'sse4.1'), + ('skylake', 'clflushopt'), ('aarch64', 'neon') ]) def test_features_query(target_name, feature): |